1. Field of the Invention
The present invention relates to a thin film transistor and an active matrix flat panel display using the same and, more particularly, to a thin film transistor and an active matrix flat panel device in which, by forming a conductive layer having multiple profiles, critical dimension (CD) bias is reduced and step coverage is enhanced.
2. Description of the Related Art
Generally, in an active matrix flat panel display, unit pixels are formed on an array substrate thereof, the unit pixels being in a matrix form in which a plurality of gate lines and a plurality of data lines are crossed. A thin film transistor, which is a switching and driving element, is formed on each pixel region.
Such an array substrate is formed through a plurality of mask processes. In particular, a conductive layer, such as a gate line, a data line, or the like, is formed using a low resistive metal, such as aluminum (Al), molybdenum (Mo), molybdenum-tungsten (MoW), or the like.
FIG. 1 is a cross-sectional view showing a conventional active matrix flat panel display. FIGS. 2 and 3 are sectional scanning electron microscope (SEM) photographs of a conventional active matrix flat panel display.
Referring to FIG. 1, active layer 120 of a polysilicon layer is formed on insulating substrate 100 on which buffer layer 110 is formed. Gate insulating layer 130 and a gate metal are deposited on an entire surface of the substrate, and the gate metal is patterned to form gate electrode 140. Impurity doping is made using gate electrode 140 as a mask to form source region 121 and drain region 125. A region in active layer 120 between source region 121 and drain region 125 acts as channel region 123.
Thereafter, interlayer insulating layer 150 is deposited and patterned to form contact holes 151, 155 which expose portions of source region 121 and drain region 125. A metal layer is deposited on the entire surface of insulating substrate 100 and is then subject to photolithography using photoresist as a mask such that source and drain electrodes 161, 165 and metal wiring 167 are formed. At this time, the width of metal wiring 167 depends on the resolution of a panel, and is generally 2 μm or more.
After source and drain electrodes 161, 165 and metal wiring 167 have been formed, passivation layer 170 is formed on the entire surface of insulating substrate 100, via hole 175 is formed on the passivation layer, the via hole exposing a portion of either source electrode 161 or drain electrode 165, for example, drain electrode 165, and pixel electrode 180 of the flat panel display is formed which is electrically connected to drain electrode 165 through via hole 175.
Subsequently, although not shown in the figure, the flat panel display is formed by a typical fabricating method for a flat panel display.
In the flat panel display formed through such processes, however, taper angle α of an edge portion of the conductive layer, such as gate electrode 140, source and drain electrodes 161, 165, metal wiring 167 or pixel electrode 180, is small, and for example from about 45° to 50°, as in FIG. 2. Critical dimension (CD) bias, namely, a difference between before and after the conductive layer, such as gate electrode 140, source and drain electrodes 161, 165, metal wiring 167, and pixel electrode 180, is etched reaches to about 0.7 μm. This is because the conductive layer is etched by performing an etching process under a condition of high retreat rate of the photoresist and, at the same time, the photoresist itself is also etched and retreated, so-called over-etched. Thus, in case of a small edge taper angle α, it is difficult to control the critical dimension (CD) bias. That is, there is a significant difference between the CDs before and after the conductive layer, such as gate electrode 140, source and drain electrodes 161, 165, metal wiring 167, and pixel electrode 180, is etched.
In the case where the CD bias is large as described above, there is a problem in that the conductive layer is formed to have its width smaller than a given width, which increases the resistance of the conductive layer.
In order to solve the above-stated problem, a method has been introduced in which the conductive layer is formed by etching the conductive layer under a condition of low retreat rate of the photoresist.
When forming the conductive layer using the etching process under the condition of the low photoresist retreat rate, edge taper angle α′ becomes large, to 80° or more, which makes it possible to form a conductive layer with its small CD bias and its width closed to a given width, as shown in FIG. 3. However, there is a problem in that the step coverage of a subsequently formed layer becomes deteriorated due to large edge taper angle α′.
That is, the edge taper angle of the conductive layer, such as gate electrode 140, source and drain electrodes 161, 165, metal wiring 167, and pixel electrode 180, acts as a factor determining the step coverage and voltage-current characteristic of a subsequently formed layer and, therefore, there is a problem in that if the edge taper angle becomes larger than a given angle, the step coverage becomes poor while if the edge taper angle becomes smaller than the given angle, the CD bias becomes larger and accordingly the resistance of the conductive layer increases, resulting in a deteriorated voltage-current characteristic.